About Exzion

Apart from being accustomed to electronics and its innovation ,I am also a Linux and open source maniac.

Verilog Program for Ring Counter with Test bench and Output

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Ring counter is a sequential circuit made up of flip flops in which the output of the final flip flop is again fed back a input to the first flip flop. The shifting operation is controlled by the clock signals. Here a 4-Bit Ring Counter is implemented and its verilog code along with the test … [Read more...]

The USB-Features and its Versions

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What is USB ? USB stands for Universal Serial Bus. It eliminates need of add-in cards and separate power supplies and its hot swapping capability allows users to easily attach and detach peripherals.They are the single most portable data backup device widely used today. A USB Flashdrive is the … [Read more...]

Paper Battery Technology

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The Idea !!! The revolutionary idea of using paper as a battery was striked to some researchers at Stanford University few yeas back and their experiments in this domain proved fruitful recently concluding that it is possible to use the plain paper as a source of power. What is Paper Battery … [Read more...]

Verilog Program for Complex Adder/Subtractor and Complex Multiplier with Test bench

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Complex Numbers are denoted in the form " a+ib " where a is the real part and b is the imaginary part. The basic rules of the complex numbers addition and multiplication are directly applicable here and can be used in the program. COMLEX ADDER & SUBTRACTOR /* Code writen by … [Read more...]

Verilog Progam for Mealy and Moore Machines with test bench and Output

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There are two types of State machines: 1)Mealy Machine 2) Moore machine The Verilog code of both machines are given below. Execute them and analyze the difference. You can download the programs at the end along with the outputs. MEALY MACHINE Mealy machine is a state machine whose … [Read more...]

Verilog Program for Implementation of Logic Function with test bench

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If you are given a logic equqtion, use the code below and implement the function: Here is the program: /* Verilog Program to implement the function f=x+y'z and Testbench for all the possible inputs using For Loop Verilog code by Vivek.R visit me @ http://vivek.techiestuffs.com contact me @ … [Read more...]

Verilog Program for 4:1 Multiplexer(MUX) with Test Bench and Output

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Multiplexer is a electronic device which used to convert many to one. It transfers the multiple inputs to a single output line by selecting one of the inputs at a time with the help of  selection lines. A 4:1 MUX has 4 inputs , 1 output and 2 selection lines. The verilog program for 4:1 MUX … [Read more...]

Verilog Program for Asynchronous D Flip Flop with Test Bench and Output

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In a Asynchronous D Flip Flop, there is no direct synchronization between the clock and the ouput as the output will change at the instant when reset value changes. The output will not wait for the positive edge or negative edge of the clock pulse as in case of Synchronous D flip flop. The … [Read more...]

Verilog program for Synchronous D Flip Flop with Test Bench and output

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Synchronous D flip flop as its name suggests its output is synchronized with the positive edge or negative edge of the clock pulse. Verilog code for this flip flop along with the test bench is given below. Download the ouput at the end. /*Synchronous D flip flop Code by Anand Contact me at … [Read more...]

VeriLog Program for JK flip Flip with test bench and Output

Verilog program for JK flip flop with the test bench is as follows. Download the outputs attached at the end. /*JK flip flop Code by Anand Contact me at [email protected] */ module jk_ff(q,qn,j,k,clk,reset); //main module// input j,k,clk,reset; output q,qn; reg q; assign qn=~q; … [Read more...]